The present invention relates in general to a semiconductor device and a method of manufacturing the same; and, more particularly, it relates to a technique that is effective in the manufacture of semiconductor devices having field effect transistors.
As one example of field effect transistors that are mounted on semiconductor devices, insulated gate field effect transistors, referred to as MISFETs (Metal Insulator Semiconductor Field Effect Transistor), have been known. Since the MISFETs have the characteristic that they can be adapted easily for high integration, they have been used generally as transistor devices constituting integrated circuits.
A MISFET generally has a constitution comprising a channel forming region, a gate insulating film, a gate electrode, a source region and a drain region. The gate insulating film is disposed to a device forming region on the main surface (device forming surface, circuit forming surface) of a semiconductor substrate, and it is formed, for example, as a silicon oxide film. The gate electrode is disposed by way of the gate insulating film on the device forming region of the main surface of the semiconductor substrate, and it is formed, for example, as a polycrystal silicon film that has been introduced with impurities for reducing the resistance value. The channel forming region is disposed in a region of the semiconductor substrate opposing the gate electrode (region just below the gate electrode). The source region and the drain region are formed of a pair of semiconductor regions (impurity diffusion regions) disposed on both sides of the channel forming region in the direction of the channel length so that the channel forming region is disposed therebetween.
A MISFET having a gate insulating film made of a silicon oxide film is usually referred to as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Further, the channel forming region is a region in which a current channel (channel) connecting the source region and the drain region is formed. Further, those devices in which current flows along the direction of the thickness (direction of depth) of the semiconductor substrate is referred to as a vertical type and those devices in which current flows in the direction of a plane (direction of surface) of the semiconductor substrate are referred to as a horizontal type. Further, those devices in which a channel for electrons (conduction channel) is formed to the channel forming region between the source region and the drain region are referred to as an n-channel conductivity type (simply as n-type), while those devices in which a channel for holes is formed thereto are referred to as a p-channel conductivity type (or simply as p-type). Further, those devices in which a drain current flows only when a voltage higher than a threshold voltage is applied to the gate electrode are referred to the an enhanced type (or E type or normally off-type), while those devices in which a drain current flows with no application of voltage to the gate electrode are referred to as depression type (or D type or normally on-type).
By the way, the size of a MISFET has become finer along with the trend toward high integration or multi-function use. In order to suppress the occurrence of a short channel effect or hot electrons along with refinement of the MISFET, an LDD structure, in which the density of impurities in the drain region on the side of the channel forming region is lowered, has been adopted in a MISFET of the sub-micron generation having a gate length of 1 (μm) or less. Since the LDD structure can decrease the amount of diffusion of the drain region to the side of the channel forming region and can ensure the size of the channel length, it can suppress the occurrence of the short channel effect. Further, since it can moderate the gradient of the impurity density distribution in the pn-junction portion that is formed between the drain region and the channel forming region to weaken the electric field intensity generated in the region, the amount of hot carriers being generated can be decreased.
A MISFET of the LDD structure is obtained mainly by forming a gate electrode by way of a gate insulating film on the main surface of a semiconductor substrate; then ion implanting impurities to the main surface of the semiconductor substrate, thereby forming a semiconductor region that is aligned with the gate electrode (extension region); then forming a side wall spacer to the side wall of the gate electrode; and then ion implanting impurities to the main surface of the semiconductor substrate so as to form a semiconductor region (contact region) being that is aligned with the side wall spacer.
On the other hand, refinement of the size of a MISFET results in an increase in the gate resistance due to a decrease of the gate length size, and an increase in the source resistance, drain resistance and contact resistance due to a shallowing of the source region and the drain region, whereby improvement for higher speed operation of a memory IC (integrated circuits), logic IC and hybrid IC having a memory function and logic function is inhibited.
In view of the above, a technique for reducing the resistance by using a refractory metal silicide film for coping with refinement and higher speed operation has been proposed. Particularly, the use of a technique for reducing the resistance, which is referred to as a salicide technique (salicide: self-alignment silicide), is effective for attaining a hybrid IC.
As a known literature relevant to the present invention, the following Patent Document 1 (Japanese Unexamined Patent Publication No. 2000-82678) is mentioned. The Patent Document 1 discloses a technique of ion implanting germanium (Ge), thereby forming source-drain regions with less junction leakage, at a high concentration and with a shallow junction.
[Patent Document 1]
Japanese Unexamined Patent Publication No. 2000-82678.